I have an upcoming interview with Apple for their SoC Verification Engineer position.
Can someone who's been through this process give me an overview of what to expect (questions/format/what to emphasize on while preparing/resources to prepare).
I have zero experience with SystemVerilog/UVM. And apart from a few internships, not much tangible work experience.
My strengths are in Verilog/Python/Comp Arch.
- Apple RQVo51Do yourself a favor, go on amazon and buy cracking digital vlsi verification interview. Understand all the question in the book and you’ll do great
- Synopsys / R&D gWqv82I had this exact interview around this time last year. The questions I was asked were mostly on UVM and verification concepts like active/passive monitors and virtual interfaces, some basic Verilog coding on a white board, and then some algorithm questions like traversing through a 3D matrix, swapping a set of elements and rotating a 2D matrix in place. Most but one interviewer were friendly and helpful during the interviews.
- TI GLVW76There are some good UVM tutorials on YouTube. Look for the ones published by Mentor, Cadence, or book authors.