How widely is C++ used in design verification?
My team is transitioning from a UVM testbench to a C++ one. I wanted to know if verification engineers prefer C++ over UVM.
TC or gtfo
There's a couple of things going for C++. HLS is one thing. If the design is in that, it's natural. System level integration is another. Being able to use the same verif env for chip, board, or system bring up/testing.
for transaction level modelling. SystemC/C++ is more efficient than SV. I.e. instructions simulator, memory model
More libraries for Design Verication? Are you planning on creating your own TLM structures?
This is exactly what I did at my last job... we created a C++ class library that modeled the UVM library..
Is your team hiring.... lol
I would stay with UVM for SV. Otherwise, by the time you are up and running with C++, you will have created 70-80% of what you already have today.
Yep, that is true.. recreating a wheel that has already been created for you. But it makes sense if there is an abstraction layer that handles communication with the simulated and/or emulated Dut. And that shim layer is in C++. Then it makes sense.
On a related note, Accellera has UVM-SystemC library available so its possible to run UVM in C++ without using systemverilog
Why ..why...why... Pick your poison
It's much faster and more libraries.