Hi I would like to know the normal TC with split for a Level 4/5 engineer (analog designer/ RTL designer/silicon validation/system design engineer) at xilinx/intel/Nvidia etc. - 10 yoe - in bay area. Could you please share? I'm not from bay area, so no idea :-)
Updated the post. Sorry, I thought all semiconductor folks will know what I'm talking about :-)
job grade 6 intel, analog design engineer, 135k TC, 4 yoe
Hey he is not the OP
Intel grade 8 is roughly 150k Iām Bay Area base + 25k bonus + some pennies like SPP and 401k matching etc. if you get close to 200k you are lucky.
Thanks a lot :-)
broadcom 11 yoe doing analog design in Bay area. Base=160k, rsu per year =144k, bonus =25% to 50% of base
very good indeed, do you have to worry about Hock layoff
I sometimes wonder when I will be forced off this gravy train š. But don't know anyone who has been layed off
Wow!! Thanks :-)
Try using english. I have no fucking idea what you are asking. rti? Si Val ?
My interpretation.. Analog designer, RTL (Logic) designer.. Silicon Validation, System Design... These are all semiconductor deisgn terms
Why would a company want to hire someone that is so lazy they canāt be fucked to ask coherent questions? Never heard someone use the term āSi Valā in my career.