Thought it would be nice to share some common interview questions in HW with answers if possible. Which companies have the hardest and easiest interview process in the industry?
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- Nvidia wooh!What is a virtual function 😂😂 . Probably every company I have interviewed with has asked this.
- Any backend VLSI position.
dynamic and static timing analysis
statistical static timing analysis and deterministic STA
slacks,jitters and skews
On chip variation AOCV, POCV
Path based approximation and Graph based approximation
clock borrowing and multi cycle paths
clock domain crossing and techniques
clock gating and clock uncertainity
PVT/RC corner and Parasitics
crosstalk, agressor-victim effects, signal integrity
SDF files and how to interpret them
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- For verification roles:Object Oriented and polymorphism, abstractions, inheritance.
Planning test bench , listing it's components and main point of interests.
Scripts and high level programming skills, logic riddles.
System level understanding of previous things you did.
Familiarity with assertions and coverage.
- Intel VINTCCan any one suggest questions on power verification? (Both pre silicon and post silicon)
- Haven't given a power specific interview yet but I wonder if they ask about upf related questions I.e. power dpmains, isolation,retention, clamping, different techniques to reduce power consumption(low voltage, adaptive voltage, clock gating etc), level-shifters, upf commands
- General high level stuff..
STA , CDC. CMOS basics, Digital Design, ASIC & FPGA design flow, Synthesis and PnR constraints, RTL debugging, netlist generation & simulation, board level debug, Low power techniques, Design for X, DFT, State Mcs, Scripting, HDL, HVL, Computer Architecture, UVM/OVM, ON CHIP and OFF CHIP protocols (AHB, AXI, CHI,...) (PCIe, DDR, Ethernet, CAN), PCB design related, SI related , Version control, sometimes AGILE and 6 sigma...
Each of above topics has multiple sub topics... need to know basics of it all.. and then specialize in few things from above...
- I have done basic level prep for most of these topics. Except AGILE, 6 sigma , PCB & protocols, DFx and DFT.
Once you prep basics... a lot of this is easy. But ONLY if you have prepared for it or studied it well at some point of time.
If you have not done that.. or forgotten.. then it is difficult.
The confidence if you know your basics is awesome.
- CDC, Sequence detector FSM, Blocking non-blocking assignment difference, fork-join
- regular expressions
pipelined uvm driver
controlling end of run phase