Want to see the real deal?
More inside scoop? View in App
More inside scoop? View in App
blind
SUPPORT
FOLLOW US
DOWNLOAD THE APP:
FOLLOWING
Industries
Job Groups
- Software Engineering
- Product Management
- Information Technology
- Data Science & Analytics
- Management Consulting
- Hardware Engineering
- Design
- Sales
- Security
- Investment Banking & Sell Side
- Marketing
- Private Equity & Buy Side
- Corporate Finance
- Supply Chain
- Business Development
- Human Resources
- Operations
- Legal
- Admin
- Customer Service
- Communications
Return to Office
Work From Home
COVID-19
Layoffs
Investments & Money
Work Visa
Housing
Referrals
Job Openings
Startups
Office Life
Mental Health
HR Issues
Blockchain & Crypto
Fitness & Nutrition
Travel
Health Care & Insurance
Tax
Hobbies & Entertainment
Working Parents
Food & Dining
IPO
Side Jobs
Show more
SUPPORT
FOLLOW US
DOWNLOAD THE APP:
ASIC Interview
- Apple not inviting for interview!!!!😥 I had an interview in 2014 with Apple. Since then I applied gazillion times and reached out to many recruiters but never received any response. What could be the reason? May be I screwed up so bad in 2014? Since that interview I upgraded my knowledge base many times over. PS: This is for ASIC PD ro
- Google asic total compensation ? asic design, pass hiring committee. Recruiter is asking for the offer expectation(and set the tone of potential lowball based on G's tradition), I did some research online and see a big variation. So asking for the opinion here. Team: Platform chip engineering, used in data center #hardware #inter
- Offers from AMD or Juniper what to chose? Hello, I have offers from AMD (Design Verification Lead) and Juniper (ASIC verification Level 4) both in bay area. Please help to decide. 1) Juniper : 233K 2) AMD : 278K Current TC: 167K (Folsom) YOE: 9 #hardware #interview #semiconductor #amd #juniper #salaries #compensation
- vote ASIC design engineer offer Synopsys vs xilinx offer eval Synopsys : location: Toronto TC:115k Canada dollar +11% Will give RSU after 1year Field: High speed IO PHY Xilinx: Location: san jose TC: 130k US dollar + 9% + 500 RSU Field : SOC IP Yoe: 3 Which is better? Which field is better? SoC or high speed IO? #hardware #semiconductor #interview
- Need help with interview prep Hi, I have an interview lined up with nvidia Position is senior ASIC design engineer Can someone help me with the prep. Pls list out the topics which might be relevant to this position. I have narrowed down to Logic design, RTL coding, cdc/rdc , upf Current Works experience 4+ years Digital Desig
- Offer from startup - Sambanova YoE: 9-10 Base: 230k Options: 250K (worth based on evaluation) Sign on: 40k Bonus: 10% TC: 320K Domain: ASIC design Current TC: 180K How does this package look? I have interviews lined up for other big companies too. But I am more interested in startups since learning and growth will be relativel
- HW interview Discord is now active I've populated it with some questions. Folks can paste or ask questions in the respective channels. Since I'm from ASIC I've only added digital design related Questions. As more folks join the quality of questions will improve. https://discord.gg/rwCDuXe If this link doesn't work, copy and open i
- Referral at Juniper Networks for ASIC Engineer Hi I am looking for ASIC Verification opportunities after a maternity break. I saw an opening at Juniper that matches my skills and experience. Would anyone please be willing to refer me ? I am finding it pretty difficult to get interview calls if I just apply online because of the break. So if an
- Is Intel hiring for new college grads? I heard that referral is the only way to get a interview call from Intel, is that really true? Do any of you have a opening for new college grad in your team? Edit: looking for a ASIC design and verification position, preferably in SF Bay Area.
- vote Should I reject my Meta offer? With Amazon's new band, my salary is expected to be more than $400k. My meta offer is as follows E5, 13yoe, $180k/$512k/15%/$50k for DV role. I cleared Google as well and Google recruiter bluntly told me they can't match meta's and it's better for me to withdraw now rather than giving me an offer a
- Microsoft Design Verification Interview Hello fellow blinders, I have an upcoming design verification interview at Microsoft. Any pointers on preparing for the interview? This would be my first interview after my current position and want to make sure I am prepared for it. Have brushed up on my experience in my current role and I am pret
- Apple HW verif with 12+ yoe plus masters Finished interview with apple and expecting an offer for Austin location. Assuming I ACE’d the interview, what is the title/band and salary I can expect in terms of base, rsu, joining bonus and relocation. I know apple RSUs vests over 4 yrs, but what are yearly merit increases, bonus, RSU refreshe
- Summer 2022 Intern Stipend One of my friend is interviewing with Nvidia and Apple for summer internship is currently in the final stages. He wants to get an idea of the current compensation ranges being offered for summer 2022 for VLSI roles (DV and ASIC Design and is doing his Master's now) Also he has 3 years of experience
- ASIC PD CAD Google India Hello guys, I have an ASIC PD CAD interview coming up this week. All rounds on same day. What kind of questions i can expect specifically (more on physical design or coding/file processing?) . I am into cadence SKILL pcell creation and layout automation (.oa). Are they specific about any language ?
- Interview preparation guidance for Electrical Engineering positions Posting for a friend: My friend is currently a Design and Verification Engineer with < 1 YOE at Sony and looking for new opportunities at top tier companies in Hardware Industry. What are the top tier companies for entry level Digital Design Verification Engineer/ Verification Engineer or ASIC D
- Looking for an experienced rtl designer as buddy I’m looking for an experienced rtl designer to give each other Verilog exercises or asic design questions, (brief interview type questions) and give feedback. I’m not actively interviewing but would like someone to be able to commit and iterate almost daily. If you are experienced, looking to prac
- NVDA IC5 offer - PD role Hi all, just got an offer from NVDA for PD role. Position and domain: PD Methodology role - Silicon PPA YOE: MS + 13yrs Grade/Level offered: IC5 Company: NVDA Location: Bay Area TC (Base + RSU + Bonus): 220k + 300k/4 + 30k Sign-on Round of negotiation: First HR verbally confirmed IC5 for this role
- NVIDIA hiring process? Whats up with NVIDIA hiring process? It seems like everytime I apply online for ASIC Engineer position, I get an automated reject email within an hour. I contacted an Nvidia recruiter and he says my Resume looks pretty good. Is there an issue with my Resume not being parsed correctly? Tried formatt
- What is Unique Design Round for FB Embedded SWE Role I have a virtual onsite coming up and recruiter mentioned I will have (title) mentioned round. Did anyone here recently went through the loop for Embedded Software Engineer interview for ASIC team & know what that means ? If you recently interviewed at FB please share your experience to probably h
- Moving from ASIC to SW I’ve been working in hardware/software for ASIC for 5 years, in the startup realm. My time is split between writing C++ for drivers and performance models and Verilog for chip design. Graduated from a top 5 CS/EE school. I enjoy the C++ a lot more, and want to move into a pure software role but am
- Reapply policy (cool-off period) in hardware/semiconductor companies Interviewing for full-time roles in RTL design, Verification, Firmware design for FPGA, ASIC, CPU, GPU. I would like to request inputs on cool-off period after interview rejection for the following hardware/semiconductor companies, before one may #reapply: 1. #intel 2. #amd 3. #broadcom 4. #med
- Google Downgrading After 11 interview over 3 months, Google HC came back with an L5 offer or a conditional L6 offer with a team match and additional interview. How common is this? Given my niche in Device driver + ASIC, finding a team match is harder. I am thinking just about putting this OFF the table given that the
- Feeling useless Completed EEE undergrad from a decent college in India, graduated with MS in CE from East Coast US in 2019. Focused on ASIC Design in MS but couldn't get any internship, subsequently no full time job and eventually had to move back to India this summer. I had no interest in Verification albeit that
- Digital Logic design for HFT I am interviewing for a digital logic design position in the high frequency trading arm of a major hedge fund. Has anyone here been directly involved in digital design for HFT? How is it for a career? My understanding is that the TC is fairly high. Is the work technically challenging and rewarding?
- Switch from HW to Sw? Trying to figure out a way if there is any chance to switch to SW. I am an ASIC design engineer with 3yrs of experience. I don’t have the educational background on CS fundamentals or programming. But lets say, I leetcode everyday, study DS and go through system design interview questions. What is t
- Request for an input in salary expectations in Digital Design domain. Currently a SoC Design Engineer at Intel (G6) in Bay Area Masters in EE: Graduated in 2015 Current comp: Base = 128k Bonus = 10k RSU = 11k Total = 149k YoE: 6+ ( 1 year in ASIC RTL + 2 years in FPGA RTL development + 3 years as SoC Design Engineer) I’m actively giving in
- not called to interviews Now I am working as AE with a solid background in Digital Design. Always was getting the higest possible scores wherever was working through my career. I would like to switch to RTL design. Recruiters would ask for resume, tell me the resume looks good and solid, send to the hiring company/manager a
- Interview Process for Digital Design Engineer at FB Reality Labs Posting for a relative of mine as he’s a a boomer. He recently got in touch with a recruiter for FB Reality Labs for a Digital Design Engineer role. https://www.metacareers.com/jobs/2280933422206464/ He’s been relatively comfortable staying at the same company for a long while now, and wants to k
- AMD Graphics Core DV Offer Evaluation Hello, I've 2 years and 6 months total DV experience. (2y3mo in India as SOC DV + 3 mo ASIC DV internship in Austin). I have received the following offer for Graphics Shader Verification engineer role at AMD, Orlando - Base - $115k Joining Bonus - $10k Reloc - $10k Stock Options - $20k over 3 years
- RTL Design Engineer Job Offer Hi All, Got a job offer from Velodyne Lidar as ASIC RTL Design engineer. Still having pending interviews for Apple and a pending offer from Cirrus Logic. Current TC: Base-125k RSU - 12k/4 LTI - 12k per year Bonus - 8-10% Offered TC: Base- 155k Bonus- 15% Stock-100k/4 50-60k performance bonus aft
- Design Verification Engineer - Returning after maternity break My wife is looking for ASIC Design Verification position. She has a Masters and professional experience of 2.5 years. She took a maternity break for 5 years and is now looking to join back into the workforce. She is taking some classes in UVM, System Verilog at an Open University. She is applying o
- Tips on DV interview at Apple I got rejected by Apple multiple times back when I was at Intel. I want to join Apple within 1 or max 2 years from now. I want to get better on subjects/Skills that Apple DV interviewers are looking for? I want to hear from Apple DV folks. What do you guys look for in a candidate during a interview.
- Switching from hardware to software I’ve worked at three FAANG companies now, 15 yoe, 550k TC. Background in ASIC design with some random embedded software, python, and GPU coding here and there but never for my main role. I’d like to transition to software in an effort to learn new things and broaden my skillset. Assume I interview
- Looking for help on Amazon/Kuiper Sr TPM role Hi I have 18 yoe in asic development and production at both rtl, sdk driver and reliabilty level. Trying to move to a more product/project related role in the FAANG domain. Cleared all interview with G. including hiring manager, but receuiter said that the req is now gone and I am left hanging look
- Salary range for a opening I would like to work for apple but before I apply and go for interview I would like to know about the salary range they can offer. My current TC is 350k and expect 400k and I am in asic design and have 17 years of experience. I don’t want to waste their time or my time. What is the best approach to
- Prep material for SW jobs Hi guys! I know there are few threads here re switching to sw roles from ASIC/hw. I am considering this option and would like to refresh my sw skills. I can dedicate 3-4 months to prepare. I am interested to know if anyone here moved to sw from HW and if you did then how you prepared for the intervi
- Qualcomm Modem Team vs AMD UMC Team I recently received offers from Qualcomm Modem team ( San Diego, CA) for Design Verification role- Modem ASIC Engineer, and another offer from AMD Unified Memory Controller ( UMC ) team ( Austin, CA) for the same role- College Graduate experience. In terms of the scalability of jobs in respective t
- Apple ASIC verification - no offer. I interviewed for an ASIC verification position at Apple. 10+ yrs experience. Intw went ok. 6 people interviwed me. I could not answer one technical question (tried but was stuck; interviwer gave me a hint but eventually moved on to the next question). There were a couple more I got stuck but figur
- vote Apple interview, will I get an offer? I interviewed with Apple. I had total 6 rounds. I felt most of the rounds went great except two. One which was slightly above average. Answered all the questions he said as satisfied by my answers and approach but at the end, he confirmed that I don’t have experience in one specific area. Then the
- Analog IC design + working visa Hi all, Recently I have moved with my family from Europe to USA ( to the same company I worked for back in Europe). Even couple years ago I had an understanding that the proposed compensation is not great, but after some time here I suspect that its pretty bad actually :) So in short: Senior Anal
- Should I jump grade or wait ? I need some opinion from people in hardware design I am a new grad (last year ) and I work in Post -Si . My interest lies in RTL (ASIC /FPGA) and my internship and thesis both are in that area. I don’t like what i am doing currently. I have an opportunity from a company for RTL design (IP design) a
- Switching from Back-end ASIC to Performance modeling/Computer Architecture/System level design. I am currently working on Physical design/Physical design methodology. Over the last couple of weeks these few points are bothering me : 1. Disparity between SW and HW engineers TC. 2. Long term future of being a HW ASIC engineer. 3. Intel as a company not looking promising. I am considering switch
- Need advice from peers to be a coder and crack sw interviews Hi there, I am an asic design engineer. I am not a strong coder but I feel it’s high time I start developing the skill set for coding and eventually move towards SW. I tried to do some leetcode but I got depressed. I figured that I do not know basics of algo and data structure. My understanding is w
- Career advice As a performance engineer/modeling engineer for hardware optimizations, where do I get the best introduction to GPU/ASIC/accelerator architecture? And also the software models. Also, I'm assuming that performance engineers are expected to be good coders. How to get hands-on C++ project experience i
- Microsoft India - Current YOE 8 Years and 7 months. Current CTC 36LPA, Offered the Same Pay at Microsoft India. I am working at a semiconductor company, the other one which can make x86_64 chips. I joined the company a month back and msft had approached me in February, but no interviews were scheduled In February. All interviews happened in April. My current Company had a 400% plus growth in last 5 years, a
- vote Broadcom/FRL offer I have two offers in DV area: Broadcom offer -San Jose Principal (icb5)- 220k/480k/50k Annual bonus 25% (55k)of base salary and multiplier for group and individual on top of it. Current group has been outstanding has multiplier Of 1.5 (~82k)on annual bonus since last 5 years. FRL - Sunnyvale -fin
- Advice for seasoned engineer I have about 22 YOE, not slowing down, sharp. Started my career in ASIC verification, low level telecommunication SW, HW design, system engineering etc. Didn't like being in a small box in a big company with lots of amateur managers trying to prove themselves, using the engineers as their stepping s
- Travel from India Any folks traveled back from India to the US recently? I am on OPT and have to travel to India urgently. Wanted to get an assessment of the situation. Thanks
- Good bootcamps for SE Job Offer I have a CS background coming out of college, but I don’t feel great about my programming abilities. Anyone have any recommendation for a bootcamp that leads to a great job offer? #engineering #software #bootcamp
- Thoughts on Jumpstart’s feature to filter candidates based on race/gender? I wonder if there even is an option to see only male, or Asian/White. Seems like Jumpstart is promoting racism and sexism in hiring.