professional environment with decent work life balance and opportunity to learn
Pay is below average and RSU refreshers almost non existent. career growth can be stagnant
Posting for my wife She joined Qualcomm 1 month ago. She interviewed with Cadence around the same time as Qualcomm but got an offer recently. Here are few details Qualcomm: Role: Post silicon system validation, mixed signal systems. base: 115k Sign on: 40k RSU: 60k over 3 years relo: 8k location:...Read more
My friend is interviewing for Principal Software Engineer position (I guess it’s called T4/L4). He has 4 yoe and PhD. What kind of compensation he can hope for in Austin? If you have Bay area numbers, please share them as well. Tagging Synopsys as cannot find Cadence. Synopsys folk can also chime i...Read more
Hi All, I have 6 years of experience in digital design verification at Intel (arizona) with current tc $166k ($125k base, $12k bonus, $29k rsu). Here’s my new offer from Cadence design systems (san jose) as application engineer for eda tool. Tc $189k Base $148k Bonus+rsu $41k matching with existing...Read more
Hello blinders. Looking for a referral in Cadence design systems for new grad role. Can someone please help me.
Is this a L7 or a L8? “Principal” sounds senior but the description of the role sounds pretty junior
Getting a full time offer from them and want to know what WLB is like. Sigrity team specifically. TC 145 #cadencedesignsystems #cadence
Looking for inputs on Cadence Design work culture, work style, comp, immigration benefits as I’m on H1b. Is it worth. Interviewing for a cloud role. TC: $200k
Can someone shed light on cadence design systems maternity leave policy?#cadencedesignsystems
This is an AE 3 role. Manager asked for TC number. YOE:5, Location: SD Dont ask for current TC because that shouldn't matter. Any caveats I should be aware of?
Hey All, Can any of you help me out with referral in Cadence Design, India. I want to shift to EDA and I currently work as ML- CAD engineer in Qualcomm. Previously worked in Intel. Thanks a lot in advance! TC:85LPA YOE: 10.5 #India #Cadence #hardware #synopsys #eda #cad
Hi, I am expecting an offer for Sr. Principal Product Engineer role at Cadence Design Systems. What should I expect? YOE: 8yrs Location: San Jose, CA Current TC: 220k
How Is The Work Life At cadence Design Systems ? How Does The Pay Look Like For Application Engineer In Austin?#hardware #interview #semiconductor #cadencedesignsystems #joboffer #technology
You can read about the company culture, pay structure, WLB and other perks online. Here are the open positions at San Jose and Austin. 1. R33329 Principal Verification Engineer - Memory Controller 2. R33481 Principal PCB Application Engineer 3. R35049 Principal Application Engineer - Analog Layout...Read more
Hello good and kind people of Blind. I have 3 offers with me and need help deciding which one to move forward with. Cadence Offer (Lead Design Engineer T3): Base - 30L, Performance Bonus - 3L, PF+Gratuity+Some random stuff - 3L, Joining Bonus - 8L, RSU - 20K usd vested in 4 years. IBM Labs (Grade...Read more
Hello, Cadence is hiring new college grads in its R&D software engineering roles. Please check this link and DM me for referrals with JobID. Would be happy to help. https://file.io/XO6rukwPAiLW #tech #software #referral #intel #cadence #synopsys #mentorgraphics #qualcomm #broadcom #nvidia #grads...Read more
Design Engineering Manager (T4 grade: 6-10 years (with Btech) or 4-8 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation activities mandatory). Job Application link: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R4...Read more
Design Engineering Manager (T4 grade: 6-10 years (with Btech) or 4-8 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation activities mandatory). Job Application link: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R4...Read more
Design Engineering Manager (T4 grade: 6-10 years (with Btech) or 4-8 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation activities mandatory). Job Application link: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R4...Read more
Design Engineering Manager (T4 grade: 6-10 years (with Btech) or 4-8 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation activities mandatory). Job Application link: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R4...Read more
#hardware #semiconductor #cadence #cadencecompensation #cadencedesignsystems #synopsys #synopsysinc #mentorgraphics #siemens