Setting a side TC (let’s assume it is the same at both companies at the moment), would you leave NVIDIA for FB as an ASIC designer Points that I need your opinion - WLB - Future career growth (in field of ASIC) - Job satisfaction - Brand name (future job change) - Company growth (stock appreciation...Read more
I am 12 yoe, currently at Qualcomm San Diego. TC is ~370k with current stock price. Skillset is HW ASIC in one of the core team. Senior staff. I got a L5 offer from Google SoC team. Location is Sunnyvale. Base 205k RSU is 550k front loaded. 33-33-22-12 Sign on 25k Basically 1st year is 400k at Goo...Read more
16 YOE IC5 @NVIDIA current TC: $480K~$500K (considering current stock growth) got this offer from FB as ASIC design E6 base: $239K bonus:20% Sign-on:$100K Init RSU: $750K I have no other offer. should I negotiate #hardware #engineer #facebookcompensation
I have two offers - Microsoft (Xbox team) and Apple (design verification). I’m trying to decide between the two. Both are very different HW roles though - at Apple it’s a traditional DV role at an ASIC team, at Microsoft it’s with a product/client facing team that requires hardware expertise. WLB, ...Read more
I got offer for hardware validation in SEG at Apple for ict3. YOE: MS + 7 yrs experience Base: 185k RSU: 200k/4 Bonus: 10% Sign on: 40k location: Bay area Do you think it's fair offer for my experience ? I don't have competing offers. My current TC is 192k and work at non-faang company. Few ...Read more
I wanted to compare ASIC DV groups of G/F/Apple in terms of TC, average stock refresh and wlb. TC: 180 Yoe: 3 Any hardware startups that can match above 3? @Apple @Google @Facebook
Base - 119k Stock- 40k/4 years Sign on- 25k + 10k(inten to FT rollover) Role - asic design Location - bay area YoE - 3 months intern at QC #MSEE #qualcomm #semiconductor #hardware
Hello folks, please help evaluate the startup offer. They have closed series B. $235k base, 10%bonus, 0.06% stock options, Location: Bay area ASIC design lead Current TC: $310K YoE: MS + 14
Can you help evaluate startup offer for asic verification position Base 200k Equit .4 % Yoe 12 Bonus no Place : sf/bayarea Current total comp is 350k ( base + stock +bonus)
Hey folks, TC : 110K Base, 40K Stock, 25K, 5K sign on and relocation package. Position : Engineer Level, ASIC group, PD role Location : Austin, TX 1 YEO Is this package is negotiable if I will get another offer ?
Hi I’m considering DV (design verification UVM) role in HFT firms here in Austin, TX. What’s is the pay range I can expect for 15 yoe experience in ASIC DV. Definitely more risky with current market conditions but want to see if the pay range is worth risk. Current TC : 300k (down more with current...Read more
Can anyone help me with Lam Research salary and designation in Bangalore for Hardware/ASIC/FPGA/Software domain for 10 yoe. #hardware #semiconductor#software Blind tax :- Yoe:-10 TC - 36L including 1 year stock options
TC: 240k, YoE: 13. HW Engineer, ASIC DV. Age mid-30's. I have been in the bay area for 10 years now. Spouse is a Ph.D student for the last 5 years and have 2 kids in elementary school. My biggest concern is my net worth is around 500k. Currently rent an apartment for ~3k. Most of the 500k is in ca...Read more
Wait Meta E5 offer from two HW teams. FRL AR/VR ML Arch and Infra Arch No numbers yet (maybe early next week). Looks like 200k base, 600k RSU, 100k sign on is typical range for HW/ASIC recently. Any comments for both team? Any strategy for negotiation with recent stock down? Update. I choose inf...Read more
Hi, I Would like to know what to expect for a ASIC RTL position @juniper. I have a MS with 4 yrs of experience. Juniper did not yet provide what grade they wanna hire me at. Current TC - 150k (Intel Santa Clara) Interested to know base, sign on and stock numbers .
Hi Guys, I've got two open offers, one at Qualcomm and one at Intel. Intel one is 30k TC lower, so didn't bother posting. What do you think I should negotiate at for the Qualcomm offer. ASIC design engineer position. 7 YOE, PhD, +other work experience Qualcomm (San Diego): Sr. Staff Base: 175k St...Read more
Hello, I've 2 years and 6 months total DV experience. (2y3mo in India as SOC DV + 3 mo ASIC DV internship in Austin). I have received the following offer for Graphics Shader Verification engineer role at AMD, Orlando - Base - $115k Joining Bonus - $10k Reloc - $10k Stock Options - $20k over 3 years...Read more
Got an offer from an Autonomous Driving startup which went public recently for ASIC Design. But I am a little concerned over the stability of the company and also I am on H1B. How would you judge a company for job security? The offer here is too tempting, but at the same time, I am scared to even c...Read more
Hi All, Got a job offer from Velodyne Lidar as ASIC RTL Design engineer. Still having pending interviews for Apple and a pending offer from Cirrus Logic. Current TC: Base-125k RSU - 12k/4 LTI - 12k per year Bonus - 8-10% Offered TC: Base- 155k Bonus- 15% Stock-100k/4 50-60k performance bonus aft...Read more
Never posted here before so not sure if this is the right format for this app. Anyway I'm trying to see what others in this field make. I don't know if I'm being paid well and i want to know how much some other companies pay. Etc. If anyones down I'd like to know: Your role, company, location How ...Read more