Apple SoC Verification On-Site Interview
I have an upcoming interview with Apple for their SoC Verification Engineer position.
Can someone who's been through this process give me an overview of what to expect (questions/format/what to emphasize on while preparing/resources to prepare).
I have zero experience with SystemVerilog/UVM. And apart from a few internships, not much tangible work experience.
My strengths are in Verilog/Python/Comp Arch.