Apple SoC Verification On-Site Interview
Hey guys! I have an upcoming interview with Apple for their SoC Verification Engineer position. Can someone who's been through this process give me an overview of what to expect (questions/format/what to emphasize on while preparing/resources to prepare). I have zero experience with SystemVerilog/UVM. And apart from a few internships, not much tangible work experience. My strengths are in Verilog/Python/Comp Arch.
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Which team? Know the basics well..they test on that ground
Have you stayed more than 6 years in your current company?
Nope. I'm just an intern.
Why does it matter if itβs more than 6 years?
I had this exact interview around this time last year. The questions I was asked were mostly on UVM and verification concepts like active/passive monitors and virtual interfaces, some basic Verilog coding on a white board, and then some algorithm questions like traversing through a 3D matrix, swapping a set of elements and rotating a 2D matrix in place. Most but one interviewer were friendly and helpful during the interviews.
This is helpful. Thank you!
Do update on how your interview goes! All the best!!
Thanks! I will update once in done with the interview!
Quick Update: It's with the SEG group. I didn't know this before π
There are some good UVM tutorials on YouTube. Look for the ones published by Mentor, Cadence, or book authors.
Thanks!
Also. I've heard that you need to get a positive feedback from all 6 interviews to get an offer. Is this true?
How many leets you done?
None. I managed to get through the first two rounds without any leetcoding. The role is mainly focused on RTL/Comp Arch and a fair bit of coding.
XOR NAND AND XOR let #i + @)(,β009! Cash.