Does hardware verification language matter in DV role for long run of career?

Hi all,
I have around 2.7+ years of experience as ASIC DV engineer. I have been working as contractor in Synopsys,India. Most of my work revolves around Systemverilog/UVM. Recently I was approached by cadence,india recuriter for DV role but works involves only c language. Is it wise to move further for cadence or not, in which HVL you worked matter in long run of career? Please guide me.

#hardware #semiconductor #DV #cadencedesignsystems #synopsys