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Which is easier; DV (C++, UVM, etc) to digital design (example in this link (micro Architecture, writing functional models, power/area/perf tradeoff etc: https://qualcomm.wd5.myworkdayjobs.com/External/job/Markham/Sr-ASIC-Design_3015738) Or vice versa?
Oh yeah DV is always open. For every 5-6 dv open positions you’ll see 1 logic position open. DV encapsulates a variety of opportunities which will always be there. So demand is more and will be. Logic is a bit less because changes doesn’t happen too much.
DV is more challenging and has more opportunities compared to design
DV to logic is good switch. PPA analysis efficiency may be little rudimentary when u start designing but u can learn on job as u attend design review meeting and take sr folks feedback. Fundamentals required are good verilog coding, basic digital structures understanding ( fifo, ram, flow ctrl, simple datapaths, latency/throughput tradeoff etc.). DM me for any technical inputs further.
Logic to DV would be very hard. DV requires a very wide range of knowledge. It would be harder to gain while you are working. DV to logic is possible but would need to gain some skills in theoretical areas. That would depend upon kind of team you are trying to move in.
Also in logic there is a lot of variation in skills and knowledge required based on experience.
So which job is more demand and opens up more opportunities for the future and job security? Sounds like DV is?