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Western Digital rd1234

May 11, 2021 36 Comments

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Hello,

I have been working in WD for 2 years in the design side. I would say the process is very slow and I haven’t got a tapeout experience since then. However it’s starting now in sometime.

Should I be looking for better opportunities or stick and finish one tape out before moving out?
And is this is a standard timeline to wait for 2 years for a tape out?

#hardware #semiconductor

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TOP 36 Comments

Renesas Electronics rnsse

Definitely not normal. Just go interview.

May 11, 2021 7 2
- Western Digital rd1234
  OP
  
  Do you think it’s better to go after a tapeout?
  
  May 11, 2021 0
- TI 7Augustine
  
  There is no harm in interviewing. Just make sure you don’t check out of your current as you start applying.
  
  May 11, 2021 0
Amazon RFPP57

What's a tapeout?

May 11, 2021 3 3
- Amazon RFPP57
  
  No, I'm an SDE. Was just curious
  
  May 11, 2021 0
- Amazon nxbhebz
  
  Ok above link is useful or imagine sending your code to customer to use but it cannot be recalled so if you messed up then you are fucked
  
  May 11, 2021 1
Apple amBored

If you are doing physical design then may be stay till tape out. With RTL design, doesn’t really matter. It is not very uncommon to not have taped out in 2 years. It all depends on the customer/application of the chip.

May 11, 2021 3 3
- Apple amBored
  
  It takes time to get familiar with the backend flow especially if you have not done PD. I was lucky where in I started with physical design before moving to RTL design. It would be good if you can get someone from physical design explain some of the basics to you. Also depending on the kind of blocks you design, you may get to experience more timing challenges, more ECOs. All that is good learning but if you want to switch and if the tapeout has been slipping then you dont need to wait. You will get more opportunities to learn those things.
  
  May 11, 2021 1
- Western Digital dot1234
  
  Thanks a ton for your inputs :)
  I truly appreciate it
  
  May 11, 2021 0
Intel ninjabot05

Wait till tapeout , coz initial RTL design is about 80% of trade , but last min full chip timing convergence , feedback , queries and ECO fixes will teach u rest of 20% of tips and tricks of trade in ASIC design. This will complete whole learning process

May 11, 2021 4 1
- Western Digital dot1234
  
  That’s a really good point
  
  May 11, 2021 0
Amazon nxbhebz

Wait till tapeout - you can’t learn that experience by paying someone !! This can only be learnt by doing it , don’t cut your foot yourself !!

May 11, 2021 4 0

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