I have onsite apple interview for design Verification role. I have 3 years experience.
What topics or subjects should I expect.
I studied SV and UVM so far. Some verilog
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One round was testing cpp skills
One was with the director who gave me design problems. Her favorite one was come up with a timing diagram at various points in the given design
OVM and testbench environment questions
One round was testing verif skills, they explained some designs and asked me how will you verify it and what would be the corner cases
Anyway, if you want a real SV/UVM job at Apple, you should target their Austin site.