Rtl design FIFO question
Hi, Could you please help me to understand and solve the below question. There are 3 FIFO, One writing at 1mbps, Second at 2 Mbps and third at 4mbps. They all need to use the same bus, first come first access, bus throughput is 8 Mbps. Each time FIFO is read 8 bytes. Find the depth of the FIFO needed to avoid overflow? Thanks @qualcomm,@nvidia,@google,@intel
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Total in flow rate is 1(in A)+2(in B) +4(in C)=7 Max out flow rate is 8 So theoretically the fifo at the output does not back pressure to cause overflow. However, you have 3 input sources, and all 3 contend for the single output. A round robin arbiter is needed, and depending on how you implement the arbiter you can have different solutions here. Consider the case where the arbiter grants the input C with 4Mbps flow rate for half the number of cycles (1/2 because it has 1/2 the flow rate of outputs), and a uniform a deterministic flow of data for that input. In this example, that input would need to buffer up 2 bytes while the arbiter is not granting input C. Similar analysis can be done for the other 2 inputs. There are many possible variation here depending on your assumptions as far as the flow rate, clock frequencies etc is concerned. The interviewer was likely looking for you to ask more questions to constraint this problem.
Here 8mbps is write throughput , not the read rate
Read the above answer carefully and frame your question properly. Write throughput for what ? Read from all fifos is same as write on the bus.