ASIC RTL design interview at Google
I have a phone interview coming up for ASIC RTL design engineer position at Google. The job description is short and bit vague to understand what I should be focusing on. Can someone share tips for how to prepare right for this one? There doesnt seem to be much discussion on the HW side of things at Google. Thanks in advance! #google#interview#hardware
Op can you share your exp post your interview ?
Sure
Edit For DV position: They asked me to code some 3 Systemverilog coding questions on Google word document and UVM theory questions about driver, sequencer connection, TLM vs analysis ports. At the end some behavioral questions. It was super easy overall
Plz do share the on-site experience once it happens. All the best
Was this for a DV position? Do they expect to have UVM knowledge for a Design position?
How many yoe do you have in Design?
3.5
You must have great resume! I have 4.5 and got rejected in 2 days after applying.. lol
I am sure you have good resume too. It’s just a more specific skill set match to what they are looking for I suppose :)
How did it go?
Care to share your experience? Thanks.
How did the interview go ?
Sync/Async FIFO design, CDC, FSM, STA and basics of logic design like FFs, gates . If you master these, you can crack any RTL design interviews.
Thanks. Yeah usually an RTL design interview is based around these concepts. I was just wondering if it’s any different with Google, since it’s a software company. There doesn’t seem to be much discussion on how the hardware side interviews of Google looks like.