Hello fellow blinders , anyone who has recently had an onsite interview with Apple in SEg for design verification ? how was the process and what areas were you tested on ? i am told that it will be a 5-6 hour process . Any insights/info will be much appreciated !
Did you clear the initial 45mins interview?? How long it take to update the result on first initial 45mins round ??
Yes I believe they let you know by 3 days max
Sv and uvm
Interviewed with them for Cambridge Mixed Signal DV team. They will ask about real number modeling / filters, UVM, brain teasers, SV assertions, testcase design and methods, as well as debugging skills and basic analog analysis. It’s a long interview and it’s rough. Something I learned a bit too late was that Apple (at least the group I interviewed with) is set up differently than I had seen before. For instance they focus on individual IP like a charge pump say, and you would verify model vs schematic for the charge pump and that charge pump would then get used throughout the designs. This changes how I would have answered the questions. The way TI is set up, you verify a whole system around the analog digital boundary not individual ip. Hope this helps you and best of luck!
Hey, Where did you give your onsite? FL?
Cambridge Massachusetts
What level/yoe?
5 yoe
How was the interview?
I gave a very good 45min interview on Monday. Still haven’t heard back. What to expect now? I answered almost everything. It was SV+UVM. Are they having in-person interviews now???? How about Covid? Or does on-site mean just video interviews?
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Used to interview with Apple SEG CAE team. About 5-6 persons. Everyone has to say yes to hire. Good luck.
Thank you ..
Do you know if the interviewee’s get a schedule beforehand? With some information on general topics/people interviewing them?