Hi all, Got a verbal offer from Xilinx San Jose team for a logic design engineer at E5 level and below are the numbers. Could you please suggest if these numbers are low, high? Thank you. Base : 130k Bonus : 9 to 10% RSU's : 750 units accounting for around 105k / 4 years Sign-on : 10k
YOE
2.5 in physical design and 2.5 in logic