Immediately looking for an open position in semiconductor ASIC Physical Design Engineering. I have the 12+ years of semiconductor professional experience, ASIC full implementation design flow which includes Synthesis, Flooeplaning, Place, Clock Tree Synthesis, Routing, PnR, Static Timing Analysis, timing closure, EM, IR, LVS, DRC, Physical Verification, Signoff Documentation, the complete flow exposure Synthesis to GDSIi. I have wide range of experienced multiple technologies from higher end to deep sub micron FinFet technology include 65nm, 16nm, 7nm, 5nm and below node. If you do see any of the open position in ASIC Physical Design, SOC Design, STA engineering then feel free to reach out me. Thank you in advance for your kind support #hardware #semiconductor #asic #vlsi #physical-design #sta
DM me if you want opportunity in Minneapolis.
Thank you for reaching out, do you know anything at Bay Area, CA.
Yeah, I checked and see some opportunities have secondary location as Bay area .
I’m assisting with the hire of many different ASIC positions in three diff states, including Bay Area, CA. Fortune 500 company. Please message me and I can help you out.
May I know how to reach you for ASIC position.
I PMed you. Please check your blind inbox
SpaceX is hiring for PD roles. Apply on linked In.
I tried there but didn’t work out
I'm also trying to get ASIC design jobs outside China. ready to relocate. Yoe 6. need sponsorship.
Where are you currently located? Would you be willing to relocate?
I’m located at Bay Area, CA. What location you have opportunity.