Never posted here before so not sure if this is the right format for this app. Anyway I'm trying to see what others in this field make. I don't know if I'm being paid well and i want to know how much some other companies pay. Etc. If anyones down I'd like to know: Your role, company, location How long you've been at this role/in the industry Salary, bonuses I do ASIC DV for Synopsys, it's a remote role. Been in the industry for 6 years, doing DV for 3 of those years. I make 135k + 10% bonus + 25K/yr stock so TC is around 175K #hardware #semiconductor #salary
Did you look at levels.fyi? Or search through old posts here? FYI synopsis doesn’t pay the highest, you might learn some information you won’t particularly enjoy.
Haven't looked there, they have HW salaries as well? I find those harder to find. How'd you know my company, when i click someone's name i don't get that info
They do have hardware as well. How do you like DV? FPGA? I'm an EE student looking to get into SWE for the better pay. How's life doing DV?
If you're in the bay you can do better. I'm sort of an applications engineer/system design engineer with 1yoe in the bay with 150 TC. With 6 yoe you can definitely do better. There's a lot of opportunities in DV in FAANG that could get you a lot more
Just read your past comment that you are able to work 1 hr a week sometimes. Stay tf where you're at you're doing awesome 😂😂
Yeah thanks lol it's not bad for right now, plus I'm in buffalo working remotely and it's really cheap here. Definitely curious what i could be making elsewhere
If it's a fully remote role, I think TC of 175 is about right for 6 years depending if you live in L/HCOL. When you get to 7 plus years is when you should start entering your prime and demand ipwards of 220-250K TC. If you like DV, you should consider getting involved with emulation to understand system level architecture etc. I feel that field is becoming more and more important.
Interesting. I've never considered that. By emulation do you mean like Veloce or something similar? Or post silicon debug?
Cadence palladium is an example where they take rtl code and pump it into a mega huge FPGA and run the chip at 1/10th the speed to ensure that silicon bugs are found. Its another form of DV and leverages all the work from DV test benches and verifies both the VIP and any assumptions at a chip and internal levels.
TC or GTFO
He's never posted here before and this is your response? Are you an asshole in real life or just on blind?
Haha yeah what the hell. Although i guess it's fair. I updated my post