Can someone please let me know about apple full panel interview ? Do they ask C , C++ questions ? What are some examples? Do they ask design Verilog questions too ? What are some examples ?
No c/c++. System verilog/UVM should suffice.
What kind of questions are asked for System Verilog/UVM ?
Some teams do ask C++ programming questions as well
They said they might ask on digital logic and design ...Can someone please let me know what all topics to cover ?
Are you a new grad?
No .. Verification engineer with 4 years experience but they asked 50% digital design questions in first round and they said they would expect digital design background too
You need to think like a designer for verification
I remember they asked me 1 verilog design question. Rest all DV. UVM, system verilog, fork join/constraints etc.
I have the same query.