Hey guys! I'm a Masters student (Computer Engineering) and I have an upcoming interview with Apple's SoC Design Verification team. I'd really appreciate if any interviewers/interviewees can share their experience. P.S. I'll be considered as an NCG (graduating this December) and I have very limited knowledge in System Verilog/UVM. I have a few internships (AMD, Juniper, Nokia) and I consider myself knowledgeable in Verilog/Computer Architecture/Digital Design.
Read the Cracking Digital VLSI Verification Interview: Interview Success by Ramdas. I’ve got a couple question directly from it.
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Why do you need to mention usc
Because you risk revealing your identity. And how does your college matter wrt the interview.