My verilog/vhdl skills are pretty good imo for rtl design. I am fairly knowledgeable about cdc and module design for someone with 1 yoe in this domain. One of my issues is that my scripting experience is simply editing what already exists and for this reason I've never bothered learning Python for real. In order to prepare for interviews should I focus on this coding weakness or prioritize building up rtl knowledge? Will being ass at Python/OOP hold me back from RTL Design Interviews? TC: won fitty
The big internet companies use more HLS than Verilog because they have more of a software mentality.
1 yoe is very early in RTL design, most knowledge comes from experience over time. You should focus on gaining more knowledge on that front, automation is useful but anyone can do it and learning curve very less. I don't believe automation will cause anyone to reject you if you show strength in the main thing that matters.
Thanks for the feedback 🙏
Good luck 👍