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Any tips on what to expect from a design verification phone screen? Would the focus be on system Verilog and UVM. Ideas, experiences? Appreciate the help
What is cam and tcam?
What’s the point to write cam and tcam... leetcode coding are needed for DV interview
Why do you say so?
CAM= content-addressable memory using sv associative array or verilog 2D arrays. TCAM = ternary CAM
Are there others who can share their interview experience as well?
Multi dimensional array randomization constraint... Like 3x3 cross 9x9.
3×3 cross 9×9.... is that in matrix multiplication context?
Think of it as memory element with unique values in each row and each column and each cube
- uvm_object vs uvm_component - write CAM & TCAM in SV.