Hello Blinders, Have an upcoming onsite interview with Apple CPU RTL team ( I think they own cache block) and comes under Silicon Engineering Group. Any inputs on the team and interview pointers? Thanks in advance. Tc: 125
OP here adding some more info: Along with whatever Microsoft mentioned above, read up on arbiter designs, circuit level designs of priority arbiters and some performance basics like bandwidth and latency concepts.
Does Apple do 2 rounds of phone screening for the cpu rtl team?
Brush up on other microarchitectural topics besides caching, such as branch prediction, prefetching, OOO execution, aside from obvious stuff like cache coherency protocols.
Thanks! You interviewed them?
Yes, but not that specific subteam